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| MCP2122 Infrared Encoder/Decoder Features * Pinout compatible with HSDL-7000 * Compliant with IrDA(R) Standard Physical Layer Specification (version 1.3) * UART to IrDA Standard Encoder/Decoder - Interfaces with IrDA Standard Compliant Transceiver * Baud Rates: - Up to IrDA Standard 115.2 Kbaud Operation * Transmit/Receive Formats (Bit Width) Supported: - 1.63 s * Low-power Mode (2 A at 1.8V, +125C) * Pb-free packaging Package Types PDIP, SOIC 16XCLK TX RX VSS 1 2 3 4 8 7 6 5 VDD TXIR RXIR RESET MCP2122 Block Diagram MCP2122 TX Encode TXIR CMOS Technology * Low-voltage operation * Extended temperature range * Low power consumption RESET Reset Logic Baud Rate Generator Decode RXIR 16XCLK RX IrDA Family Selection Baud Rate Device Host UART IR Encoder / Decoder Yes Yes Yes Yes Yes Protocol Layer Handler No No IrCOMM(3) IrCOMM(3) IrCOMM(3) Clock Source XTAL 16XCLK XTAL XTAL XTAL Host UART Baud Rate Selection HW/SW By 16XCLK None - Fixed HW HW Host UART easily interfaces to a PC's serial port (DTE) Host UART easily interfaces to a modem's serial port (DCE) Extended Temperature Range (-40C to +125C) Comment MCP2120 2400 2400 312,500 (1) 312,500 (1) MCP2122 2400 2400 115,200 (1) 115,200 (1) MCP2140 9600 9600 MCP2150 9600 9600 115,200 (2) 115,200 (2) MCP2155 9600 9600 115,200 (2) 115,200 (2) Note 1: The host UART and the IR operate at the same baud rates. 2: The host UART and IR baud rates operate independent of each other. 3: Supports the 9-wire "cooked" service class of the IrCOMM Application Layer Protocol. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 1 MCP2122 NOTES: DS21894C-page 2 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 1.0 DEVICE OVERVIEW TABLE 1-1: The MCP2122 is a stand-alone IrDA standard encoder/ decoder device that is pinout-compatible with the Agilent(R) HSDL-7000 encoder/decoder. The MCP2122 has two interfaces: the host UART interface and the IR interface (see Figure 1-1). The host UART interfaces to the UART of the Host Controller. The Host Controller is the device in the embedded system that transmits and receives the data. The IR interface connects to an infrared (IR) optical transceiver circuit that converts electrical pulses into IR light (encode) and converts IR light into electrical pulses (decode). This IR optical transceiver circuit could be either a standard infrared optical transceiver (such as a Vishay(R) TFDU 4300) or it could be implemented with discrete components. For additional information, please refer to AN243, "Fundamentals of the Infrared Physical Layer" (DS00243). When the Host Controller transmits the UART format data, the MCP2122 receives this UART data and encodes (modulates) it bit by bit. This encoded data is then output as electrical pulses to the IR transceiver. The IR transceiver will then convert these electrical pulses to IR light pulses. The IR transceiver also receives IR light pulses (data), which are outputted as electrical pulses. The MCP2122 decodes (demodulates) these electrical pulses, with the data then being transmitted by the MCP2122 UART. This modulation/demodulation method is performed in accordance with the IrDA standard. Table 1-1 shows an overview of some of the device features. Figure 1-1 shows a typical application block diagram. Table 1-2 shows the pin definitions of the MCP2122 during normal operation. MCP2122 FEATURES OVERVIEW MCP2122 UART, IR 16XCLK Yes 8-pin PDIP 8-pin SOIC Features Serial Communications: Baud Rate Selection: Low-power Mode: Packages: Infrared Technology Features: * Universal standard for connecting portable computing devices * Effortless implementation * Economical alternative to other connectivity solutions * Reliable, high-speed connection * Safe to use in any environment; can even be used during air travel * Eliminates the hassle of cables * Allows PCs and non-PCs to communicate with each other * Enhances mobility by allowing users to easily connect 1.1 Applications Some applications where an IR interface (MCP2122) could be used include: * * * * * * Data-Logging/Data Exchange System Setup System Diagnostic Read Out Manufacturing Configuration Host Controller Firmware Updates System Control FIGURE 1-1: SYSTEM BLOCK DIAGRAM Host Controller PIC(R) MCU Host UART Interface Protocol Handler MCP2122 TX Encode TXIR IR Optical Interface Transceiver TFDU 4300 TXD SO UART SI RESET Clock (I/O) 16XCLK RX Decode Reset Logic Clock Logic RXIR RXD (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 3 MCP2122 TABLE 1-2: Pin Name 16XCLK TX RX VSS RESET PIN DESCRIPTION Pin Number PDIP 1 2 3 4 5 SOIC 1 2 3 4 5 Pin Type I I O -- I Buffer Type ST ST -- P ST Description 16x external clock source input Asynchronous receive from Host Controller UART Asynchronous transmit to Host Controller UART Ground reference for logic and I/O pins Resets the Device H = Normal Operation L = Device in Reset Asynchronous receive from infrared transceiver Asynchronous transmit to infrared transceiver Positive supply for logic and I/O pins RXIR TXIR VDD Legend: ST I P O 6 7 8 = = = = 6 7 8 I O -- ST -- P Schmitt Trigger input with CMOS levels Input Power Output DS21894C-page 4 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 2.0 DEVICE OPERATION TABLE 2-1: Input Pin Name RESET State L The MCP2122 is a low-cost infrared encoder/decoder. The baud rate is the same for the host UART and IR interfaces and is determined by the frequency of the 16XCLK signal, with a maximum baud rate of 115.2 Kbaud. The MCP2122 is made up of these functional modules: * Clock Driver (16XCLK) * Reset * IR Encoder/Decoder - IrDA Standard Encoder - IrDA Standard Decoder The 16XCLK circuit allows a clock input to provide the device clock. The Reset circuit supports an external reset signal. The IR Encoder logic takes a data bit and converts it to the IrDA standard signal according to the IrDA standard Physical Layer specification, while the IR Decoder logic takes the IrDA standard signal and converts it to 8-bit data bytes. DEFAULT OUTPUT PIN STATES IN DEVICE RESET Output Pin State RX H TXIR L Device in Reset mode Comments TABLE 2-2: DEFAULT OUTPUT PIN STATES AFTER DEVICE RESET (RESET = LH) Output Pin State RX -- TXIR LH After 7 - 8 16XCLK L pulses, the TXIR pin will pulse high. L -- -- After 4 16XCLK pulses, RX = L. Comments Input Pin Name State TX L H RXIR L H -- HL H 2.1 Power-up As the device is powered up, there will be a voltage range in which the device will not operate properly. The device should be reset once it has entered the normal operating range (from an out-of-voltage condition). The RESET pin may then be forced high. Other device operating parameters (such as frequency, temperature, etc.) must also be within their operating ranges when the device exits reset. Otherwise, the device may not function as desired. 2.3 Decoupling 2.2 Device Reset It is highly recommended that the MCP2122 have a decoupling capacitor (CBYP). A 0.01 F capacitor is recommended as a starting value, but an evaluation of the best value for your circuit/layout should be performed. Place this decoupling capacitor (CBYP) as close to the MCP2122 as possible (see Figure 2-1). The MCP2122 is forced into the known state (RESET) when the RESET pin is in the low state. Once the RESET pin is brought to a high state, the device begins normal operation (if the device operating parameters are met). Table 2-1 shows the states of the output pins while the device is in reset (RESET = Low). Table 2-2 shows the state of the output pins once the device exits reset, RESET = LH (device in Normal Operation mode). The MCP2122 has a RESET noise filter in the RESET input signal path. The filter will detect and ignore small pulses. Using the RESET pin to enter a low-power state is discussed in Section 2.9 "Minimizing Power". FIGURE 2-1: VDD DEVICE DECOUPLING MCP2122 VDD VSS RESET 16XCLK TX RX CBYP (bypass capacitor) TXIR RXIR (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 5 MCP2122 2.3.1 BROWN-OUTS FIGURE 2-4: VDD VDD R1 Q1 R2 40 k RESET Some applications may subject the MCP2122 to a brown-out condition. Good design practice requires that when a system is in brown-out, the system should be in reset to ensure that the system is in a known state when the system exits the brown-out. This brown-out circuitry is external to the MCP2122. EXTERNAL BROWN-OUT PROTECTION CIRCUIT 2 2.3.1.1 External Brown-Out Reset Circuits Figure 2-2 shows a circuit for external brown-out protection using the TCM809 device. Figure 2-3 and Figure 2-4 illustrate two examples of external circuitry that may be implemented. Each option needs to be evaluated to determine if they satisfy the requirements of the application. MCP2122 Note 1: This circuit is less expensive, but less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD * R1 R1 + R2 = 0.7V FIGURE 2-2: EXTERNAL BROWN-OUT PROTECTION USING THE TCM809 VDD VDD 2: Resistors should be adjusted for the characteristics of the transistor. TCM809 RST VSS RESET MCP2122 FIGURE 2-3: VDD EXTERNAL BROWN-OUT PROTECTION CIRCUIT 1 VDD 33 k 10 k 40 k Q1 RESET MCP2122 Note 1: Resistors should be adjusted for the characteristics of the transistor. 2: This circuit will activate reset when VDD goes below (Vz + 0.7V), where Vz = Zener voltage. DS21894C-page 6 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 2.4 16XCLK (Bit Clock) The MCP2122 requires an external clock source to operate. The 16XCLK pin is the device clock input (see Figure 2-5) and is independent of the host UART interface or the IR interface. The 16XCLK determines all timing during device operation. It is the edge of the 16XCLK pin that causes activity to occur. The 16XCLK signal can also be referred to as a bit clock (BITCLK). There are 16 BITCLKs for each bit time. The BITCLKs are used for the generation of the Start bit, the eight data bits and the Stop bit. When the embedded system could be receiving IR communication, the MCP2122 is required to have the 16XCLK signal clocking at the expected frequency, with minimal variation in that frequency. Between data bytes (Stop bit to Start bit), the 16XCLK frequency can be changed. This may occur in systems where the Host Controller is implementing one of the IrDA standard application layer protocols (such as IrObex). When the embedded system does not want to receive IR communications, the 16XCLK clock can be disabled (static). This will reduce the power consumption of the system. Figure 2-6 shows the relationship of the 16XCLK signal to the RXIR input, which then determines the RX output signal. Figure 2-7 shows the relationship of the 16XCLK signal to the TX input, which then determines the TXIR output signal. For device timing information, refer to Section 4.0 "Electrical Characteristics". FIGURE 2-5: DEVICE CLOCK SOURCE MCP2122 16XCLK FIGURE 2-6: 16XCLK AND RX/RXIR 16 16XCLK 16 16XCLK 16XCLK (input) 3 CLK RXIR (input) RX (output) 16 16XCLK Bit A Bit B FIGURE 2-7: 16XCLK AND TX/TXIR 16 16XCLK 16 16XCLK 16XCLK (input) TX (input) 16 16XCLK TXIR (output) Bit A 3 CLK ( ~ 4 s) Bit B (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 7 MCP2122 2.4.1 BAUD RATE 2.5 Encoder/Decoder The baud rate for the MCP2122 is determined by the frequency of the 16XCLK signal. Equation 2-1 demonstrates how to calculate the 16XCLK frequency based on the desired baud rate. Table 2-3 shows some common baud rates and the corresponding 16XCLK frequency. The IR encoder/decoder is made up of two major components. They are: * IR Decoder * IR Encoder The encoder receives UART data (bit by bit) and outputs a data bit in the IrDA standard bit format. Figure 2-8 shows a functional block diagram of the encoder. The decoder receives IrDA standard data (bit by bit) and outputs data in UART data bit format. Figure 2-8 shows a functional block diagram of the decoder. The encoder/decoder has two interfaces. They are: * Host UART interface * IR interface EQUATION 2-1: 16XCLK FREQUENCY F 16XCLK = 16 * (Desired Baud Rate) TABLE 2-3: Baud Rate 9600 19,200 38,400 57,600 115,200 COMMON BAUD RATE/ 16XCLK FREQUENCY Comment 16XCLK Frequency (F16XCLK) 153,600 307,200 614,400 921,600 1,843,200 2.5.1 ENCODING (MODULATION) Each bit time is comprised of 16 bit clocks. If the value to be transmitted (as determined by the TX pin) is a logic-low, the TXIR pin will output a low level for 7-bit clock cycles, a logic-high level for 3-bit clock (with a maximum high-time of about 4 s) cycles, with the remaining time (6-bit clock cycles or more) being low. If the value to transmit is a logic-high, the TXIR pin will output a low level for the entire 16 bit clock cycle. 2.5.2 DECODING (DEMODULATION) Each bit time is comprised of 16 bit clocks. If the value to be received is a logic-low, the RXIR pin will be a low level for the first 3-bit clock cycle (or a minimum of 1.6 s), with the remaining time (13-bit clock cycles) being high. If the value to be received is a logic-high, the RXIR pin will be a high level for the entire 16-bit clock cycle. The level on the RX pin will be in the appropriate state for an entire 16-bit clock cycle. FIGURE 2-8: MCP2122 RECEIVE DETECT TO ENCODER/DECODER BLOCK DIAGRAM RX Decode TX Encode Glitch Filter RXIR Pulse Width Limiter (~ 4 s) TXIR The following table shows the state on the RESET pin and how this effects the operation of the TXIR pin. RESET State VIH VIL TXIR output encoded value of TX pin TXIR is forced low Comment DS21894C-page 8 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 2.5.3 ENCODING AND SCREEN CAPTURES TABLE 2-4: Baud Rate 9600 19200 38400 57600 115200 TXIR HIGH PULSE WIDTH TXIR Pulse Width Table 2-4 shows the TXIR pin high-time at different common baud rates. The internal TXIR pulse-width high-time limiter is a feature that minimizes the system current consumption at lower baud rates. The IrDA standard specification requires that optical receiver circuitry detect pulses as narrow as 1.41 s (1.63 s is the typical time at 115200 baud). Therefore, the time that the TXIR pin is high after this valid detection is additional current that is driven by the emitter LED. The MCP2122 will force the TXIR pin low once the pulsewidth limiter has timed out. Figure 2-9 shows the MCP2122 16XCLK, TX and TXIR waveforms at 115200 baud for a single TX low bit. In this case, the TXIR is high for three 16XCLK pulses. In Figure 2-10, the MCP2122 is at 9600 baud for a single TX low bit. In this case, the TXIR is high for 3.55 s (determined by pulse-width limiter circuit). 3xT16XCLK Circuit 19.53 s (1) 9.77 s (1) 4.88 s (1) 3.26 s 1.63 s Pulse-width Limiter (2) Circuit 4.00 s 4.00 s 4.00 s 4.00 s 4.00 s Actual Pulse Width 4.00 s (3) 4.00 s (3) 4.00 s (3) 3.26 s 1.63 s Note 1: The pulse-width limiter on the TXIR pin saves system current for this baud rate. 2: This TXIR pulse width time is a design target and is not tested. Actual times may be greater than, or less than, this value. 3: This time (determined by the pulse-width limiter circuit) is device dependent. FIGURE 2-9: MCP2122 AT 115200 BAUD WAVEFORM TXIR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B Jitter of the TX input relative to the 16XCLK and TXIR 16XCLK Pulse (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 9 MCP2122 FIGURE 2-10: MCP2122 AT 9600 BAUD WAVEFORM TXIR 12 345 6 7 8 9 10 11 12 13 14 15 16 16XCLK Pulse A B Jitter of the TX input relative to the 16XCLK and TXIR DS21894C-page 10 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 2.6 Host UART Interface 2.7 IR Interface The UART interface is used to communicate with the Host Controller. Though a UART is capable of a fullduplex interface, the direct coupling to the IR encoder/ decoder allows only half-duplex operation (since the IR side is either receiving or transmitting and not both at the same time). This means that the system can't transmit and receive at the same time. The IR interface is used to communicate with the optical receiver circuitry. The IR interface is either transmitting data or receiving data (half-duplex). 2.8 Encoding/Decoding Jitter and Offset 2.6.1 TRANSMITTING Figure 2-11 shows the jitter on the RXIR and TX pins, along with the offset on the RX pin and the TXIR pin. Jitter is the possible variation of the desired edge. Figure 2-9 and Figure 2-10 show the jitter of the TX pin (range is indicated by red dashed lines). Offset is the propagation delay of the input signal (RXIR or TX) to the output signal (RX or TXIR). Figure 2-9 and Figure 2-10 show the offset of the TXIR pin from the 16XCLK signal that starts the bit time. When the controller sends serial data to the MCP2122, the baud rates are required to match. There will be some jitter on the detection of the high-tolow edge of the start bit. This jitter will affect the placement of the encoded start bit. All subsequent bits will be 16 BITCLK times later. While RXIR is receiving data (low pulse), the TXIR pin is disabled from transmitting. 2.6.2 RECEIVING 2.9 Minimizing Power When the controller receives serial data from the MCP2122, the baud rates are required to match. There will be some jitter on the detection of the high-tolow edge of the Start bit. This jitter will affect the placement of the decoded Start bit. All subsequent bits will be 16 BITCLK times later. The TXIR pin is disabled when data is being received (low pulse) on the RXIR pin. The device can be placed in a low-power mode by forcing the RESET pin low. This disables the internal state machine. To ensure that the lowest power consumption is obtained, ensure that the 16XCLK pin is not active and that the other input pins (TX and RXIR) are at a logic-high or logic-low level. 2.9.1 RETURNING TO OPERATION When returning to normal operation, the RESET pin must be forced high and the 16XCLK signal should be operating. Time should be given to ensure that the 16XCLK is stabilized at the desired frequency before data is allowed to be transmitted or received. FIGURE 2-11: EFFECTS OF JITTER AND OFFSET 16 16XCLK 16 16XCLK BITCLK 3 16XCLK RXIR RX Jitter RX TX Jitter TX TX Offset 3 16XCLK 16 16XCLK TXIR RX Offset 16 16XCLK (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 11 MCP2122 NOTES: DS21894C-page 12 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 3.0 DEVELOPMENT TOOLS Features: * 8-pin socket for installation of MCP2122 (installed) and 14-pin socket for installation of MCP2120 * Three Optical Transceiver circuits (1 installed) * Headers to interface to low cost PICDEM Demo Boards, including: - * PICDEMTM HPC Explorer Demo Board - * PICDEMTM LCD Demo Board - * PICDEMTM FS USB Demo Board - * PICDEMTM 2 Plus Demo Board * Headers to easily connect to the user's embedded system * Jumpers to select routing of MCP212X signals to the PICDEMTM Demo Board Headers * Jumpers to configure the operating mode of the board The MCP212X Developer's Daughter Board is used to evaluate and demonstrate the MCP2122 or the MCP2120 IrDA(R) Standard Encoder/Decoder devices. A header allows the MCP212X Developer's Daughter Board to be jumpered easily into systems for development purposes. The MCP212X Developer's Daughter Board is designed to interface to several of the "new" low cost PIC(R) Demo Boards. These include the PICDEM HPC Explorer Demo board, the PICDEM FS USB Demo board, and the PICDEM LCD Demo board. When the MCP212X Developer's Daughter Board is used in conjunction with the PICDEM HPC Explorer Demo board, the MCP212x can be connected to either of the PIC18F8772's two UARTs or the RX and TX signals can be "crossed" so the MCP212x device can communicate directly out the PICDEM HPC Explorer Demo Board's UART (DB-9). (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 13 MCP2122 NOTES: DS21894C-page 14 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 4.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient Temperature under bias ........................................................................................................... -40C to +125C Storage Temperature ............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +6.5V Voltage on RESET with respect to VSS ..................................................................................................... -0.3V to +14V Voltage on all other pins with respect to VSS ................................................................................. -0.3V to (VDD + 0.3V) Total Power Dissipation (1) ...................................................................................................................................800 mW Max. Current out of VSS pin ..................................................................................................................................500 mA Max. Current into VDD pin .....................................................................................................................................500 mA Input Clamp Current, IIK (VI < 0 or VI > VDD) ................................................................................................................... 20 mA Output Clamp Current, IOK (V0 < 0 or V0 > VDD)............................................................................................................. 20 mA Max. Output Current sunk by any Output pin..........................................................................................................25 mA Max. Output Current sourced by any Output pin.....................................................................................................25 mA Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. NOTICE: (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 15 MCP2122 FIGURE 4-1: VOLTAGE-FREQUENCY (16XCLK) GRAPH, -40C TA +125C 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 1.8 0 1.8432 4 Frequency (MHz) DS21894C-page 16 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 4.1 DC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Characteristic Supply Voltage Supply Current (2) DC Characteristics Param. No. D001 D010 Sym VDD IDD Min 1.8 -- Typ (1) -- 0.1 Max 5.5 1 Units V mA Conditions See Figure 4-1 FOSC = 1.8432 MHz, VDD = 5.5V (TX = H, RXIR = H) Transmitter (TX = L, RXIR = H) FOSC = 1.8432 MHz, VDD = 1.8V (4) FOSC = 1.8432 MHz, VDD = 5.5V Receiver (RXIR = L, TX = H) FOSC = 1.8432 MHz, VDD = 1.8V (4) FOSC = 1.8432 MHz, VDD = 5.5V VDD = 1.8V (4) VDD = 5.5V -- -- -- -- D020 IPD Device Disabled Current (3) -- -- -- -- -- -- -- -- 300 1 500 2 2 4 A mA A mA A A Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: The supply current is mainly a function of the operating voltage and frequency. Pin loading, pin rate and temperature have an impact on the current consumption. a)The test conditions for all IDD measurements are: 16XCLK = external square wave, from rail-to-rail; TX = VSS, RXIR = VSS, RESET = VDD. 3: The device disable current is mainly a function of the operating voltage. Temperature also has an impact on the current consumption. When the device is disabled (RESET = VSS). The test conditions for all IDD measurements are: 16XCLK = external square wave, from rail-to-rail; TX = VSS, RXIR = VDD, RESET = VSS; The output pins are driving a high or low level into infinite impedance. 4: These parameters (shaded) are characterized but are not tested. These values should be used for design guidance only. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 17 MCP2122 DC Characteristics (Continued) Standard Operating Conditions (unless otherwise specified) Operating temperature -40C TA +125C (extended) Operating voltage VDD range as described in DC spec, Section 4.1 "DC Characteristics". Min Typ (1) Max Units Conditions DC CHARACTERISTICS Param No. Sym VIL Characteristic Input Low-Voltage Input pins TX, RXIR RESET 16XCLK D031 D032 D033 VIH D041 D042 D043 IIL D060A D061 D060B IIH Vss Vss Vss -- -- -- -- 0.2 VDD 0.2 VDD 0.2 VDD V V V Input High-Voltage Input pins TX, RXIR RESET 16XCLK Input Leakage Current (2, 3) TX and 16XCLK RESET RXIR -- -- -- -- -- -- 1 1 1 A A A VSS VPIN VDD, Pin at high-impedance VSS VPIN VDD VDD = 5.5V, VRXIR = VDD 0.8 VDD 0.8 VDD 0.8 VDD -- -- -- VDD VDD VDD V V V Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as coming out of the pin. DS21894C-page 18 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 DC Characteristics (Continued) Standard Operating Conditions (unless otherwise specified) Operating temperature: -40C TA +125C (Extended) Operating voltage VDD range as described in DC spec, Section 4.1 "DC Characteristics". Characteristic Output Low-Voltage RX TXIR VOH D090B D091 Output High-Voltage RX (2) TXIR (2) Capacitive Loading Specs on Output Pins D101A D101B COUT CIN All Output pins All Input pins -- -- -- 7 50 -- pF pF TA = +25C, FC = 1.0 MHz VDD - 0.7 VDD - 0.7 -- -- -- -- V V IOH = -0.8 mA, VDD = 1.8V IOH = -0.8 mA, VDD = 1.8V -- -- -- -- 0.6 0.6 V V IOL = 2 mA, VDD = 1.8V IOL = 2 mA, VDD = 1.8V Min Typ (1) Max Units Conditions DC CHARACTERISTICS Param No. D080B D081 Sym VOL Note 1: Data in the Typical ("Typ") column is based on characterization results at +25C. This data is for design guidance only and is not tested. 2: Negative current is defined as coming out of the pin. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 19 MCP2122 4.2 4.2.1 Timing Parameter Symbology and Load Conditions TIMING CONDITIONS The timing parameter symbols have been created following one of the following formats: The temperature and voltages specified in Table 4-2 apply to all timing specifications, unless otherwise noted. Figure 4-2 specifies the load conditions for the timing specifications. TABLE 4-1: SYMBOLOGY 2. TppS T Time 1. TppS2ppS T F Frequency E Error Lowercase letters (pp) and their meanings: pp io Input or Output pin rx Receive bitclk RX/TX BITCLK Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low xclk tx RST Oscillator Transmit Reset P R V Z Period Rise Valid High-impedance TABLE 4-2: AC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40C TA +125C (Extended) Operating voltage VDD range as described in DC spec, Section 4.1 "DC Characteristics". AC CHARACTERISTICS FIGURE 4-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS PIN VSS CL CL = 50 pF for all output pins 7 pF (typical) for all input pins DS21894C-page 20 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 4.3 Timing Diagrams and Specifications EXTERNAL CLOCK TIMING FIGURE 4-3: Q4 16XCLK Q1 Q2 Q3 Q4 Q1 1 3 3 4 4 TABLE 4-3: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 4.1 "DC Characteristics" Characteristic Min Typ(1) -- -- -- -- -- Max -- 1.8432 2 -- 7.5 Units ns MHz % ns ns Note 5 Conditions AC Characteristics Param. No. 1 1A Sym TXCLK FXCLK External 16XCLK Period (2, 3) 542.5 External 16XCLK DC Frequency (2, 3) -- 1C EXCLK Clock Error (4, 5) 50 3 TXCLKL, Clock in (16XCLK) TXCLKH Low or High Time -- 4 TXCLKR, Clock in (16XCLK) TXCLKF Rise or Fall Time (5) Note 1: Data in the Typical ("Typ") column is at 5V, +25C, design guidance only and are not tested. Note 5 unless otherwise stated. These parameters are for 2: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 3: A duty cycle of no more than 60/40 (High-Time/Low-Time or Low-Time/High-Time) is recommended for external clock inputs. 4: This is the clock error from the desired clock frequency. The total system clock error includes the error from the transmitter and the error of receiver (from the desired clock frequency). If the transmitter is 2% fast from the target frequency, and the receiver is 2% slow from the target frequency, the total error is 4%. 5: These parameters (shaded) are characterized but are not tested. These values should be used for design guidance only. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 21 MCP2122 FIGURE 4-4: I/O WAVEFORM 16XCLK RX or TXIR Pin Old Value 20, 21 New Value Note: Refer to Figure 4-2 for load conditions. TABLE 4-4: I/O TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 4.1 "DC Characteristics" Characteristic RX pin rise time (2, 3) TXIR pin rise time (2, 3) AC Characteristics Param. No. 20A 20B 20C 20D 21A 21C Sym ToR Min -- -- -- -- -- -- Typ (1) 10 10 10 10 10 10 Max 25 60 25 60 35 25 Units ns ns ns ns ns ns Conditions VDD 2.7V (Note 3) VDD = 1.8V (Note 3) VDD 2.7V (Note 3) VDD = 1.8V (Note 3) Note 3 Note 3 ToF RX pin fall time (2, 3) (2, 3) TXIR pin fall time Note 1: Data in the Typical ("Typ") column is at 5V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: See Figure 4-2 for loading conditions. 3: These parameters (shaded) are characterized but are not tested. These values should be used for design guidance only. DS21894C-page 22 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 FIGURE 4-5: VDD RESET 30 Internal RESET 34A TXIR Pin RX Pin 34B 34B 34A RESET AND DEVICE RESET TIMER TIMING TABLE 4-5: RESET AND DEVICE RESET TIMER REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 4.1 "DC Characteristics". Characteristic RESET Pulse Width (low) Default output state of TXIR pin from RESET Low Default output state of RX pins from RESET Low Min 2000 -- -- Typ (1) -- -- -- Max -- 2 2 Units ns s s Conditions VDD = 5.0 V AC Characteristics Param. No. 30 34A 34B Sym TRSTL ToD ToD Note 1: Data in the Typical ("Typ") column is at 5V, +25C unless otherwise stated. These parameters are for design guidance only and are not tested. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 23 MCP2122 FIGURE 4-6: TX AND TXIR WAVEFORMS Bit IR100 16XCLK TX IR114 IR113 IR122 IR120 IR115 TXIR IR121 0 1 0 0 1 0 IR122 IR122 IR122 IR122 IR122 IR113 Bit Bit Bit Bit ... TABLE 4-6: TX AND TXIR REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 4.1 "DC Characteristics". Characteristic Min Typ (1) Max Units Conditions AC Characteristics Param. No. IR100A IR100B IR102A IR102B IR113 Sym TTXBIT TTXIRBIT ETXBIT ETXIRBIT TTXRF Transmit Baud Rate -- 16 -- Transmit Baud Rate 16 -- 16 Host UART TX Error -- -- 2 TXIR Error from 16XCLK -- 0 -- TX pin rise time and fall -- -- 25 time -- -- 1 IR114 TTXPDIRJ 16XCLK to TX jitter 7 -- 8 IR120 TTXL2TXIRH TX falling edge () to TXIR rising edge () (1) IR121A TTXIRPW TXIR pulse width 3 -- 3 1.41 3.5 5 IR121B IR122 TTXIRP TXIR bit period (1) -- 16 -- IR123 TTXIRRF TXIR pin rise time and fall -- -- 10 time Note 1: Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise design guidance only and are not tested. TXCLK TXCLK % Note 2, 3 % Note 2, 4 ns Note 2 TXCLK Note 2 TXCLK TXCLK At 115200 baud s At 9600 baud (Note 5) TXCLK ns 50 pF load (Note 2) stated. These parameters are for 2: These parameters (shaded) are characterized but are not tested. These values should be used for design guidance only. 3: The TX pin operation may be asynchronous to the 16XCLK pin. This is the error from the desired baud rate for the system. 4: The TXIR pin operation is synchronous to the 16XCLK pin. Any error present on the 16XCLK pin (Parameter 1C) will be refelected on the TXIR pin. 5: This specification is not tested. This value is from the design target. DS21894C-page 24 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 FIGURE 4-7: 16XCLK AND THE TX AND TXIR WAVEFORMS 16 CLK Data bit x 16XCLK IR114 Bit Value to TX 0 IR113 IR122 IR115 TXIRI (3 * 16XCLK pulses) IR121A TXIR Time Out IR121B TXIR pin IR123 IR121C IR124 6 CLK IR113 1 16 CLK Data bit x+1 TABLE 4-7: TX AND TXIR REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 4.1 "DC Characteristics". Characteristic Min Typ (1) -- -- -- Max 25 1 8 Units Conditions ns Note 2 TXCLK Note 2 TXCLK AC Characteristics Param. No. Symbol IR113 TTXRF TX pin rise time and fall time -- TX to 16XCLK jitter -- IR114 TTXJ IR120 TTXL2TXIRH TX falling edge () to 7 TXIR rising edge () (1) TTXIRPW TXIR pulse width Smaller of IR121A 3 1.41 IR121B IR122 TTXIRP TXIR bit period -- 20C TTXIRR TXIR pin rise time -- -- 20D 21C TTXIRF TXIR pin fall time -- Note 1: Data in the Typical ("Typ") column is at 5V, +25C, design guidance only and are not tested. Smaller of -- 3 TXCLK At 115200 baud 3.5 5 s At 9600 baud (Note 3) 16 -- TXCLK 10 25 ns VDD 2.7V (Note 2) 10 60 ns VDD = 1.8V (Note 2) 10 25 ns Note 2 unless otherwise stated. These parameters are for 2: These parameters (shaded) are characterized but are not tested. These values should be used for design guidance only. 3: This specification is not tested. This value is from the design target (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 25 MCP2122 FIGURE 4-8: RXIR AND RX WAVEFORMS Bit IR110 16XCLK IR133 IR132 RXIR IR131A IR134 IR130 IR132 RX IR103 0 IR103 1 0 0 1 0 IR132 IR132 IR132 IR132 IR132 IR132 IR132 IR132 IR132 IR132 Bit Bit Bit Bit ... Note: Refer to Figure 4-2 for load conditions. TABLE 4-8: RXIR REQUIREMENTS Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40C TA +125C (Extended) Operating Voltage VDD range is described in Section 4.1 "DC Characteristics". Characteristic Min Typ (1) -- 0 -- -- 4 3 Max 2 -- 25 16 -- -- Units % % ns Conditions Note 2, 3 Note 2, 4 AC Characteristics Param. No. Sym IR101A ERXIRBIT IR101B ERXBIT IR103 TTXRF RXIR Error -- Host UART RX Error -- RX pin rise time and fall -- time Receive (RX pin) Bit Rate 16 IR110 TRXBIT -- IR130 TRXIRL2RXH RXIR Low AND 16XCLK edge ( or ) to RX falling -- edge () RXIR pulse width 1.41 IR131A TRXIRPW (1) RXIR bit period -- IR132 TRXIRP IR133 TRXIRJ 16XCLK to RXIR jitter -- 16XCLK to RX skew -- IR134 TRXSKW RXIR Filter 0.7 IR135 TRXPDFIL Note 1: Data in the Typical ("Typ") column is at 5V, +25C, design guidance only and are not tested. TXCLK TXCLK At 115,200 baud TXCLK At 9600 baud -- 3 TXCLK s 16 -- TXCLK -- 1 TXCLK Note 2 -- 2.5 s -- 1.4 s Note 5 unless otherwise stated. These parameters are for 2: These parameters (shaded) are characterized but are not tested. These values should be used for design guidance only. 3: The RXIR pin operation is asynchronous to the 16XCLK pin. This is the error from the desired baud rate for the system. 4: The RX pin operation is synchronous to the 16XCLK pin. Any error present on the 16XCLK pin (Parameter 1C) will be refelected on the RX pin. 5: The minimum specification ensures that ALL pulses less then this pulse width are rejected, the maximum specification ensures that ALL pulses greater than this pulse width are never rejected, and pulse widths between these may or may not be rejected. DS21894C-page 26 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 5.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables are not available at this time (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 27 MCP2122 NOTES: DS21894C-page 28 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 6.0 6.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP2122 E/P e3 256 0706 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: MCP2122 E/SN 3 0706 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 29 MCP2122 8-Lead Plastic Dual In-Line (P or PA) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 D 3 E A2 A A1 e b1 b L c eB Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .290 .240 .348 .115 .008 .040 .014 - MIN INCHES NOM 8 .100 BSC - .130 - .310 .250 .365 .130 .010 .060 .018 - .210 .195 - .325 .280 .400 .150 .015 .070 .022 MAX .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-018B DS21894C-page 30 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 8-Lead Plastic Small Outline (SN or OA) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 b h c h A A2 A1 L L1 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.17 0.31 5 5 0.25 0.40 - 1.25 0.10 MIN MILLIMETERS NOM 8 1.27 BSC - - - 6.00 BSC 3.90 BSC 4.90 BSC - - 1.04 REF - - - - - 8 0.25 0.51 15 0.50 1.27 1.75 - 0.25 MAX 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 31 MCP2122 FIGURE 6-1: EMBOSSED CARRIER DIMENSIONS (12 MM TAPE) Top Cover Tape A0 W K0 B0 P TABLE 6-1: Case Outline SN CARRIER TAPE/CAVITY DIMENSIONS Package Type SOIC .150" 8L Carrier Dimensions W mm 12 P mm 8 A0 mm 6.4 Cavity Dimensions B0 mm 5.2 K0 mm 2.1 Output Quantity Units 3300 Reel Diameter in mm 330 FIGURE 6-2: SOIC DEVICE User Direction of Feed Pin 1 Pin 1 W, Width of Carrier Tape P, Pitch Standard Reel Component Orientation Reverse Reel Component Orientation DS21894C-page 32 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 APPENDIX A: REVISION HISTORY Revision C (February 2007) * Updated Development Tools section * Update packaging outline drawings * Updates Product Identification System section. Revision B (September 2004) * Undocumented changes Revision A (June 2004) * Original release of this document (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 33 MCP2122 NOTES: DS21894C-page 34 Preliminary (c) 2007 Microchip Technology Inc. MCP2122 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - X /XX Package Examples: a) b) c) MCP2122-E/P: MCP2122-E/SN: MCP2122T-E/SN: Extended Temperature, 8L-PDIP package Extended Temperature, 8L-SOIC package Tape and Reel, Extended Temperature, 8L-SOIC package Temperature Range Device MCP2122: Infrared Encoder/Decoder MCP2122T: Infrared Encoder/Decoder, Tape and Reel E = -40C to +125C Temperature Range Package P = Plastic DIP (300 mil, Body), 8-lead SN = Plastic SOIC (150 mil, Body), 8-lead (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 35 MCP2122 NOTES: DS21894C-page 36 Preliminary (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2007 Microchip Technology Inc. Preliminary DS21894C-page 37 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 12/08/06 DS21894C-page 38 Preliminary (c) 2007 Microchip Technology Inc. |
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